搜索结果: 1-15 共查到“知识库 VLSI”相关记录83条 . 查询时间(0.06 秒)
High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m)
Cryptography Logical Effort Gaussian Normal Basis multiplication
2016/12/8
In this paper, by employing the logical effort technique an efficient and high-speed VLSI implementation of the digit-serial Gaussian normal basis multiplier is presented. It is constructed by using A...
VLSI Implementation of Double-Base Scalar Multiplication on a Twisted Edwards Curve with an Efficiently Computable Endomorphism
Multiple-precision arithmetic Pseudo-Mersenne prime
2015/12/30
The verification of an ECDSA signature requires a double-base scalar multiplication, an operation of the form k⋅G+l⋅Q where G is a generator of a large elliptic curve group of prime order ...
Configuration of VLSI Arrays in the Presence of Defects
Circuit area fault tolerance percolation theory probabilistic analysis queuing processes systolic arrays
2015/8/14
The penalties for configuring VLSI arrays for yield enhancement are assessed. Each dement of the fabricated array is assumed to be defective with independent probability p. A fixed fractmn R of the el...
Configuration of VLSI Arrays in the Presence of Defects
Circuit area fault tolerance percolation theory probabilistic analysis queuing processes systolic arrays wafer-scale integration wire length
2015/8/12
The penalties for configuring VLSI arrays for yield enhancement are assessed. Each dement of the fabricated array is assumed to be defective with independent probability p. A fixed fractmn R of the el...
On Detection, Analysis and Characterization of Transient and Parametric Failures in Nano-scale CMOS VLSI
Automatic Test Pattern Generation Crosstalk Design-for-Testability Integrated Circuit Intermittent Failure Soft Error
2014/11/7
As we move deep into nanometer regime of CMOS VLSI (45nm node and below), the device noise margin gets sharply eroded because of continuous lowering of device threshold voltage together with ever incr...
二维提升小波的VLSI结构设计及FPGA验证
JPGA2000 小波变换 并行结构 提升算法
2014/3/24
针对JPEG2000中小波变换的硬件实现占用资源量大、速度慢等问题,提出了一种有效的二维小波硬件实现模型。该模型采用流水线并行结构,即对图像中各行像素进行流水线处理的同时,对小波分解的各级采用并行结构处理。这样的结构提高了小波变换的处理速度,实现了实时处理,节省了硬件的片上存储及外部存储资源。用FPGA对此模型进行验证。验证实验采用Xinlinx公司的SPARTEN-3系列芯片,对1 024×2 ...
Hardware Oriented Algorithm Analysis and Modification for High Definition AVS Video Encoder VLSI Implementation
Hardware Oriented Algorithm Analysis Modification High Definition AVS Video Encoder
2010/12/21
In AVS video coding standard, some algorithms consume huge computation with relatively little coding performance contribution, and some algorithms create data dependencies that are harmful for efficie...
Hardware Oriented Algorithm Analysis and Modification for High Definition AVS Video Encoder VLSI Implementation
Hardware Oriented Algorithm Analysis Modification High Definition AVS Video Encoder
2010/12/21
In AVS video coding standard, some algorithms consume huge computation with relatively little coding performance contribution, and some algorithms create data dependencies that are harmful for efficie...
Efficient Macroblock Pipeline Structure in High Definition AVS Video Encoder VLSI Architecture
Efficient Macroblock Pipeline Structure AVS Video Encoder VLSI Architecture
2010/12/21
In traditional four-stage pipeline structures for H.264 video encoder hardware implementation, rate distortion optimization (RDO) based mode decision was turned off, and
dual-port or ping-pang on-chi...
High Throughput VLSI Architecture for Multiresolution Motion Estimation in High Definition AVS Video Encoder
VLSI Architecture Multiresolution Motion Estimation Video Encoder
2010/12/21
This paper proposes a hardware friendly multiresolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and...
一类易于VLSI实现的对称双正交小波设计方法研究
对称双正交小波 格形结构 双正交滤波器组 线性相位
2010/4/12
该文提出了一类对称双正交小波的设计方法。该类双正交小波的小波滤波器组具有格形结构，实现该小波变换的分析滤波器组和综合滤波器组满足双正交条件和正则性条件，且设计的各滤波器均为实数二进制系数，因而该小波变换易于高速VLSI实现。文中的理论推导和设计实例，均验证了该设计方法的有效性。
基于多水平方法，设计并实现了一种VLSI剖分系统（Multilevel-based VLSI Partitioner，MVP）。介绍了MVP系统的结构框图、处理流程及模块功能。MVP系统的多水平剖分程序引入图核到粗化阶段，谱图论到初始剖分阶段，群智能到投影优化阶段，得到了无向赋权图更优的剖分。MVP系统特点体现在VLSI线网到无向赋权图的转换，避免了剖分算法直接在VLSI线网上进行剖分，提高了VL...
VLSI-cell placement technique for Architecture of Field Programmable Gate Array (FPGA) design
Field Programmable Gate Array (FPGA) Space Vector Pulse Width Modulation (SVPWM) Configurable Logic Blocks (CLBs)
2010/1/11
The Field Programmable Gate Array (FPGA) is an on field programmable device which can be designed for different applications. Various types of software are available for its synthesis. The cell placem...
VLSI平面布图规划中模拟退火算法的加速策略
布图规划 模拟退火 加速
2009/12/10
布局是现代VLSI物理设计中十分关键的步骤，而模拟退火等智能算法在针对宏模块布局的平面布图规划问题中得到广泛应用。针对应用于VLSI平面布图规划的模拟退火算法进行了研究和分析，并针对布图本身特性在退火算法中采用了一种导向性的邻域构造策略来加速算法的收敛，有效地提高了平面布图规划中模拟退火算法的搜索效率。
低I/O带宽高性能运动估计VLSI结构的设计
视频编码 运动估计 超大规模集成电路（VLSI）
2009/10/22
在视频编码的运动估计运算中，全搜索结构最为主流，然而相应传统的全搜索1-D、2-D脉动结构或树形结构在计算的过程中，往往会出现I/O带宽大或计算效率低等问题。针对这些问题，提出一种新的数据流和相应的两维脉动阵列结构，利用相邻当前块搜索域的数据重合，在保证高性能的同时最大程度地减小I/O带宽。结果表明，提出的结构可以在256周期内完成一个宏块41个运动矢量计算，并且只有3个数据输入。