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We describe the global optimization of phase-locked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An a...
In this paper, the effect of the variation of amplitude and the chopping period of a PWM signal on the stability of a closed-loop control for a DC motor drive is investigated. First, the entire system...
This paper describes the design and fabrication of a Ka Band PLL DRO having a fundamental oscillation frequency of 19.250 GHz, used as local oscillator in the low-noise block of a down converter...
Based on the structure proposed in [1] and [2],two new types of parallel decision feedback loops are presented. Efforts are made to secure the data transition and relax the delay limitation for the in...

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