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Academy of Mathematics and Systems Science, CAS Colloquia & Seminars：Quantum State and Gate Verification with Minimum Settings
最小设置 量子态 门验证
2023/4/14
Efficient verification of quantum states and gates is crucial to the development of quantum technologies. Although the sample complexities of quantum state verification and quantum gate verification h...
Breach the Gate: Exploiting Observability for Fault Template Attacks on Block Ciphers
Fault attacks PRESEN
2019/8/19
Fault attacks (FA) are one of the potent practical threats to modern cryptographic implementations. Over the years the FA tech- niques have evolved, gradually moving towards the exploitation of device...
Improvements for Gate-Hiding Garbled Circuits
garbled circuits Yao's protocol private function evaluation
2017/10/9
Garbled circuits have been highly optimized for practice over the last several years. Today's most efficient constructions treat different types of gates (e.g., AND vs XOR) differently; as such, they ...
Reducing Garbled Circuit Size While Preserving Circuit Gate Privacy
garbled circuits private function evaluation
2017/2/20
Yao's garbled circuits have been extensively used in Secure Function Evaluations (SFE). Several improvements have been proposed to improve the efficiency of garbled circuits. Kolesnikov and Schneider ...
Gate-scrambling Revisited - or: The TinyTable protocol for 2-Party Secure Computation
implementation secure two-party computation
2016/7/14
We propose a new protocol, nicknamed TinyTable, for maliciously secure 2-party computation in the preprocessing model. One version of the protocol is useful in practice and allows, for instance, secur...
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths --- Toward Efficient CBC-Mode Implementation
AES hardware architectures unified encryption/decryption processors
2016/6/8
This paper proposes a highly efficient AES hardware architecture that supports both encryption and decryption for the CBC mode. Some conventional AES architectures employ pipelining techniques to enha...
Identification of a reversible quantum gate: assessing the resources
Identification reversible quantum gate assessing resources
2016/1/23
We assess the resources needed to identify a reversible quantum gate among a finite set of alternatives, including in our analysis both deterministic and probabilistic strategies. Among the probabilis...
Quantum homomorphic encryption for circuits of low $T$-gate complexity
quantum cryptography public-key cryptography secret-key cryptography
2015/12/30
Fully homomorphic encryption is an encryption method with the property that any computation
on the plaintext can be performed by a party having access to the ciphertext only.
Here, we formally defin...
When the virtual influences reality. The conservation project of the Toledo Gate in Ciudad Real (Spain)
Virtual Archaeology reconstruction hypothesis 3D model
2015/9/11
The Toledo Gate of Ciudad Real, Spain, constructed between the late 13th and early 14th centuries, is the last remaining portion of a
once complete medieval city wall. It represents the long history ...
An Architecture for Electrically Configurable Gate Arrays
Architecture Electrically Configurable Gate Arrays
2015/8/14
An Architecture for Electrically Configurable Gate Arrays.
A CMOS Electrically Configurable Gate Array.
A new statistical model for routing of gate arrays is described. The model takes into consideration the effect of gate utilization on wiring area requirement. Model computed wiring area estimates sugg...
A Low-Power Field-Programmable Gate Array Routing Fabric
Field-programmable gate arrays (FPGAs) lowpower performance analysis routing architecture/fabric
2015/8/12
This paper describes a new programmable routing fabric for field-programmable gate arrays (FPGAs). Our results show that an FPGA using this fabric can achieve 1.57 times lower dynamic power consumptio...
An efficient method for large-scale gate sizing
Combinational logic circuits geometric process circuit
2015/8/10
We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimum allowed...
3d Modelling of The Market Gate of Miletus developed From Photogrammetric Evaluations
Photogrammetry 3D-Visualisation CAD
2015/7/14
After rediscovery in 1903 the impressive Market Gate of Miletus was transported to the Pergamon Museum in Berlin (Germany) in
1907/08. In 1929/30 the object was rebuilt in the original dimensions (ab...